1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to various methods of controlling Vss implants on memory devices, and a system for performing same.
2. Description of the Relatrd Art
Flash memory devices are a type of EEPROM (Electrically Erasable Programmable Read-Only Memory). The term xe2x80x9cflashxe2x80x9d refers to the ability of the memory to be erased in blocks. As in other non-volatile memory devices, flash memory devices typically store electrical charges, representing data, in transistors having either a floating gate or a charge trapping dielectric. The stored charges affect the threshold voltage of the transistors. For example, in an n-channel floating gate transistor, an accumulation of electrons in the floating gate electrode creates a high threshold voltage in the transistor. The presence or absence of the stored charge can be determined by whether current flows between a source region and a drain region of the transistor when appropriate voltages are applied to the control gate, source and drain.
While there are myriad ways of configuring flash memory devices, in one common configuration sometimes called a NOR architecture, the drain regions of each memory cell (transistor) have a contact and are connected in rows forming bit lines in a conductive layer that runs above the memory cell stacks. The conductive layer can be, for example, a first metal layer. Source regions are typically connected by Vss lines running parallel to the word lines and leading to a common ground. The Vss lines are formed by doping the semiconductor substrate.
This configuration has proven useful in building compact, high-speed flash memory devices, however, there has been a continuous demand to further reduce the size of these devices. In further reducing the size of flash memory devices, the resistance in Vss lines has become an issue. As attempts are made to make smaller devices, it is found that the amount and depth of doping required to adequately lower resistance along Vss lines cannot be introduced without causing short channel effects. Thus, there has been an unsatisfied need for methods of further reducing the Vss resistance in flash memory devices without causing short channel effects.
The process of forming such Vss lines involves performing an implant process over an area that contains a number of exposed or empty trenches. For the Vss line to serve its intended function, it is important that this implant process be performed correctly such that the desired doped regions are formed in the substrate. However, using existing technology, variations in the resulting implant regions may occur due to a variety of factors. As a result of the variations, the electrical characteristics of the doped regions may not meet target performance characteristics. For example, the implant regions for the Vss lines may exhibit an increase in resistance in cases where, due to various factors, the doped region is not properly formed. As a result, the performance characteristics of the resulting memory device may not meet required performance specifications.
The present invention is directed to various methods and systems that may solve, or at least reduce, some or all of the aforementioned problems.
The present invention is generally directed to various methods of controlling Vss implants on memory devices, and a system for performing same. In one illustrative embodiment, the method comprises forming a plurality of trenches in a semiconducting substrate, measuring at least one physical characteristic of at least one of the trenches and determining at least one parameter of a Vss implant process to be performed on the substrate based upon the measured at least one physical characteristic of at least one trench. In further embodiments, the method comprises performing the Vss implant process comprised of the determined at least one parameter on the substrate. In some cases, the measured physical characteristic of the trench is comprised of at least one of a depth, an opening width, a sidewall angle and a profile of the trenches. In other cases, the present invention may be used to control or determine the dopant dose, implant energy and/or implant angle of the Vss implant process.